管理机制的支持使用TLBTranslationlookasidebuffer.PPT

In the previous two slides, I have shown you that for both read and write operation, the access time is much shorter than the DRAM cycle time (use the time line).. The DRAM cycle time puts a limit on how frequent can you initiate an access. The access time tells us how quickly will you get what you want once you start your access. much shorter than the cycle time. What would you do if you are the little football-fan? Well, I know what I will do. I will go to see Olympic-game. So if he is smart, he can see Olympic-game every 4x years and then see World-cup. The scheme he just invented is memory interleaving. Another performance booster for DRAM is fast page mode operation. In normal DRAM, we can only read and write M-bit at time because only one row and one column is selected at any time by the row and column address. In other words, for each M-bit memory access, we have to provided a row address followed by a column address. Very time consuming. So the engineers get smart and say: wait a minute, this is silly, why don‘t we put a N x M register here so we can save an entire row internally whenever we access a row? Virtual Machine ISA support Impact of Virtual machines on Virtual Memory and I/O Virtual memory Physical memory Machine memory Shadow page table/TLB The Xen Virtual machine Virtual Machine Monitor Virtual machine monitor(VMM) or Hypervisor Managing software Managing hardware Requirements Guest software should behave on a VM exactly as if it were running on the native hardware, except for performance-related behavior or limitations of fixed resources shared by multiple VMs. Guest software should not be able to change allocation of real system At least two processor modes, system and user. A privileged subset of instructions that is available only in system mode, resulting in a trap if executed in user mode. All system resources must be controllable only via these instructions. Cloud Computing Instead, the memory system of a modern computer con