基于并联取小时钟结构的ECL时序电路设计研究-电路与系统专业论文.docxVIP

Ab Ab stract In this dissertation，we mainly discussed the design method of ternary ECL sequential circuits．The new clock structure 一parallel-or clock structure was presented to design different types of latches and triggers．Also，we use the state trigger to design sequential circuits． First，after analyzing its principle and electric character,we introduced the former improvement about the ECL circuits，especially the algorithm of switch level ECL circuits design characterized by the Boundary_addition—Minimization structure，and complemented the algorithm． Then，based on the algorithm of switch level ECL circuits design characterized by the Boundary_addition—Minimization structure，we analyzed the characteristic of the D latch，and designed the new ternary D latch with the parallel-or clock structure． We also designed the temary T latch，ternary principal and subordinate trigger and duplicate D latch，and gave the Pspice simulations．The difference of principle between the new and old clock structure was analyzed then． At last，the behavior of the sequential circuits Was analyzed，and the state trigger was used to design the sequential circuits．The sequential circuits were designed based the parallel-or clock structure．The issues in the flow,for example，the reverse state coding were analyzed to compare the difference between the new and old design method，Then the design flow was described by examples。 Key words：ECL circuits；Multivalued Logic；sequential circuit；switch level；clock structure；D latch；state trigger；reverse state coding 第一章绪论二值信号(0，1)被广泛的应用在传统数字电路中，它容易实现信号的识别及 第一章绪论 二值信号(0，1)被广泛的应用在传统数字电路中，它容易实现信号的识别及 生成，有最简单的电路结构，最强的抗干扰能力，最可靠的工作性能。但是它携 带数字量少，相应空间和时间利用率低n1。为了解决这个问题，1921年由Postt2J 提出第一个对任何基数均满足完备性的代数系统，以后又以此为基础逐渐发展成 为多值格代数。从70年代起国际上已经对多值逻辑进行了有组织的系统研究， 并取得了一系列成就∞“1，多值逻辑的研究受到国内外的广泛关注与重视，对于 多值逻辑的研究具有非常广泛的意义。 ECL(Emitter—Coupled Logic)电路，即射极耦合逻辑电路，是一种非饱和型 数字逻辑电路砖1。由于晶体管工作在非饱和态，消除了限制速度提高的晶体管存 储时间，ECL电路具有很高的工作速度，平均延迟时间可达到几个毫微秒甚至亚 毫微秒数量级哺1，在超高速数字系统中具有广泛的应用。 基于以上多值逻辑与ECL电路的优点