集成电路低功耗测试方法研究-检测技术与自动化装置专业论文.docxVIP

熊成电路低功耗测斌方靛研究；摘要摘要 熊成电路低功耗测斌方靛研究；摘要 摘要 燧着工芝豹发镤灏集成电路娥模豹扩丈，功耗已残为煞戏电路设诗中钓～个十分关 蕤熬鹚题，搀绕黪低礁耗设诗主装围绕歪喾王俘获态簿凄态功耗麴毽诗秘毯建震开。溅 试技术是Ic设计的重要环节，丽在测试期间，电路有较移的跳变从而产生疑多的功耗， 进耐会影响被测器件的可靠馈和产晶的成品率，低功耗测试l|益成为研究的热点。本文 主瑟磅究测试功耗瓣谬毡和优化以及与之相必魏阉题。 针对上述阍遂，本文主要开鼹了班下三方掰静工俸： 1+波形模拟和故障模拟。基于布尔过稷的组合波形横拟器不仪能用于逻辑功能的 模季敛，丽且麓反殃瞻路定豺信息浆波形模掇，英具有精度巍、快这、门级、数量纯豹优 点e鍪于该波澎模羧器，使矮靛穗为UMCF豹中嗣迄爨舔式，本文避一步建立了毂艨 模拟嚣，使质实骥的并行故转模拟器具有逋艘抉，代码量少簿特点。 2，扫描链功耗估计与优化。针对广泛使用的扫描测试技术，提出了～种基于概率 分辑黥扫接链秘态功栽溪型。该模燮胃瘸于溺试臻耗懿镶速绩诗，著可避一步震予测试 功耗优化。稿描测试期闯功耗主黉来自测试良凝移入、移嬲扫描链时写l越盼功耗及强锻 描测试期间的组合电路部分消糕的功耗。本文利用概率统计的方法对扫描测试功耗建横 进考亍溺试功耗估诗，并与抟统鹩摸按方法进行了晓较，在不簿低精确凄黪憾援下，髅计 遮溪褥刭较大撵费。并在照墓醚上通过鞭《试陶爨帮挡箍攀元瓣序方法采降低扫疆溅试臻 耗，敬得很始的敲粜。 3．低功耗BIST技术。低功耗BIST是低功耗测试领域较热门的研究方向，各种方 寨既覆辍开镱、涎试效率蠢功稔氇不露，奉文裁娄菰疆究魏拣送行了滚入努耩器详缀分 类。并就各种情况下的应用提供了解决方案。 关键键；霹溪淫设计，努撵瓣瀵，凌态凌嚣，瞧功耗嚣试 集成电路低功耗测试方法研究：Abstract 集成电路低功耗测试方法研究：Abstract Research on VLSI Low Power Testing Technology Chen Zhigno(Testing Technology and Automatic Equipment) Directed By Xie Wenkal Abstract The complexity ofcurrent generation ICs，combined with rapidly developing high density,high speed packaging and reduced design cycle time，has made it extremely difficult and expensive to comprehensively test electronic systems，and diagnose failed parts using traditional methods．This situation worsens as we move toward nanometer technologies．The reduced device geometries．increased operating speed and very low power supply levels，are reducing noise margins and component reliability,complicating defect behavior and increasing the impact of timing，cross talk，transient，and other spurious faults．Power consumption during normal operation and test application becoming increasingly important，low power design only address power dissipation during normal operation．Moreover power consumption during test application must be taken into consideration．Therefore．there iS a great need for innovative advances in test and diagnosis methodologies to cope with these problems． In this dissertation．we present some original ideas for problems above． 1．Boolean proc