基于FPGA的数字锁相环设计.PDFVIP

30 1 Vol130 No11 2009 1 M ICROCOMPUTER APPLICAT IONS Jan12009 FPGA 1, 2 1 杨莉荣 王 炜 1 2 ( 300160 065000) : VH L, , ; FPGA PLL, : FPGA VHDL Design of D igital Phase- Locked Loop Based on FPGA 1 2 1 YANG Lirong ,WANGW ei 1 ( Schoolof Information and Communication Engineering in T ianjin Polytechnic University, T ianjin, 300160, China 2H ebeiTechnicalCollege ofPetroleum Profession, Langfang, 065000, China) Abstract: igital phase- locked Loop( PLL) technology will be used w idely1This paper has proposed a methodology of designing PLL, systematically states its operational principlewhich is followed by the designing processes and smi ulating results of the main modules1Thismethodology, based on VH L technique, can be mi plemented by field programmable logic array( FPGA) 1 K eywords: igitalPhase- Locked Loop, FPGA, VH L , [ 1] , , , ,, [2] FPGA ,, 2 ( PLL),(EXOR), (LPF), (VCO)() f v , (f R ), ud ( t),, u ( t ), VCO, c f v f R , f v =f R , uV ( t)uR ( t) (), 2008- 09- 22 1 : FPGA 69 3 [2] , 1 K( K )/ NK 1 /Mf 0 2Nf 0, f 0 M N 2 2Nf 0 H (H = M /2N) , , , 4 FPGA 41 : [ 3] ,