面向TTA架构处理器的编译器技术的研究与实现-计算机应用技术专业毕业论文.docxVIP

、ABSTRACT 、 Since theωnfigurable processor can be customized 岛r a particular application， it 1 has increasingly being used in the embedded system design.ηl?s 也esis presents a method of the ∞mpiler back-end optimization for the configurable and extensíble |叫 神 (‘， processors b剧创 on the Tran叩ort Trigger叫Architecture (TTA).ηle designs and implements of register allocation with linear scan algorithm inωmpil町 optimization 缸e explained. In addition， the 也esis presents a new method of how ωcombine register allocation and instruction scheduling，and has made an implernentation. At present，∞mpil配 for general-purpose processor has been ableωgenerate v，町 efficientωde. But most of the compil町 technology is only for a fixed struc阳re. 80 it is a big challenge in ∞de optimization for ωnfigurable processor，and 批 is also a difficult and important task 岛r 也e application of configurable processor. Compiler esp∞ially 阳back咽d design is 由e key of TTA processor being used widely. A compilers back-end optimizing design for TTA processor using linear scan algorithm ís presented in 也扭曲创is. This algori由mhωbeen usedωaccomplish global regíst时 allωation. The implemantation of 也is algorithm on TTA ∞mpil町 h槌 many advantages，such 部 hlgh quality ofωde and easy implernentation， etc. The advantages of 也is algorithm are e叩ecially obvious when source programs con阳讪 large number of variablesωmpeting for 伽 limited number of registers for storage. In 时dítion， the 也esis presents the s阳dy of a series of optimization b剧创 on linear scan algorithm. Instruction schαiuling is another important step in theωmpil町 back咽d desi阴， and 由e processing s叫uence between register allocation and instruction scheduling is the key factors for compi1er performance. The thesis also proposes a method of combiníng regist即 allocation and instruction scheduling. By findíng a balance point between instruction scheduling and register allocation whlch are restricted by each other，也e quality of the ∞de is impoved. This