课件：verilog设计可综合的状态机的指导原则.ppt

【13.16】八位计数器设计实例之一 module counter1( out, cout, data, load, cin, clk); output [7:0] out; output cout; input [7:0] data; input load, cin, clk; reg [7:0] out; always @(posedge clk) if( load ) out = data; else out = out + cin; assign cout=( out) cin; //只有当out[7:0]的所有各位都为1 //并且进位cin也为1时才能产生进位cout endmodule 【13.16】八位计数器设计实例之二 module counter2( out, cout, data, load, cin, clk); output [7:0] out; output cout; input [7:0] data; input load, cin, clk; reg [7:0] out, preout; reg cout; always @(posedge clk) out = preout; always @( out or data or load or cin ) begin {cout, preout} = out + cin; if(load) preout = data; end endmodule 带异步高电平有效的置/复位端的D触发器实例 module dff2( q, qb, d, clk, set, reset); input d, clk, set, reset; output q, qb; reg q, qb; always @(posedge clk or posedge reset ) if(reset) begin q=0; qb=1; end else if(set) begin q=1; qb=0; end else begin q=d; qb=~d; end endmodule 同步高电平有效的置位/复位端的D触发器 module dff2( q, qb, d, clk, set, reset); input d, clk, set, reset; output q, qb; reg q, qb; always @(posedge clk) if(reset) begin q=0; qb=1; end else if(set) begin q=1; qb=0; end else begin q=d; qb=~d; end endmodule THANK YOU SUCCESS * * 可编辑 13.2 典型状态机实例 宇宙飞船控制器 宇宙飞船控制器 just_launched is_landed abort_mission all_systems_go clk launch_shuttle land_shuttle start_countdown start_trip_meter cnt 13.2 典型状态机实例 宇宙飞船控制器 just_launched is_landed abort_mission /launch_shuttle=1 /land_shuttle=1 /start_trip_meter=1 HOLD SEQUENCE LAND LAUNCH ON_MISSION cnt=0 /start_countdown=1 all_systems_go module statemachine ( launch_shuttle, land_shuttle, start_countdown, start_trip_meter, clk, all_systems_go, just_launched, is_landed, cnt, abort_mission); output launch_shutt