实验二加法器的设计与仿真小强.docxVIP

实验二加法器的设计与仿真 一、 实验内容 用VHDL语言设计全加器; 利用设计的全加器组成串行加法器； 用VHDL语言设计并行加法器。 二、 VHDL程序 全加器 library ieee; use ieee.std」ogic_1164.all; entity f_adder is port( x.^cin: in stdjogic; s,cout: out stdjogic); end f_adder; architecture bhv of f_adder is begin s=x xor y xor cin; cout=(x and y)or(x and cin)or(y and cin); end bhv; 四位串行加法器 library ieee; use ieee.std_logic_1164.all; entity ffadder is port(x,y: in std」ogic_vector(3 downto 0); cin: in stdjogic; s: out std」ogic_vector(3 downto 0); cout: out stdjogic); end ffadder; architecture bhv of ffadder is signal outl,out2,out3: stdjogic; component f_adder is port(x,y,cin: in stdjogic; s,cout: out stdjogic); end component f_adder; begin ul: f_adder port map(x(0),y(0),cin,s(0),outl); u2: f_adder port map(x(l),y(l),outl,s(l),out2); u3: f_adder port map(x(2),y(2),out2,s(2),out3); u4: f_adder port map(x(3)zy(3)/out3,s(3)/cout); end bhv; 74283： 4 位先行进位全加器(4-Bit Full Adder) library ieee; use ieee.stdjogic_1164.all; entity fulladder is port(x;y: in stdjogic_vector(3 downto 0); cin: in stdjogic; s: out stdjogic_vector(3 downto 0); cout out stdjogic); end fulladder; architecture bhv of fulladder is signal c: std_togic.vector(4 downto 0); signal g,p: stdjogic_vector(3 downto 0); begin g(0)=x(0) andy(0); g(l)=x(l) andy(l); g(2) =x(2)andy(2); g⑶=x(3) and y⑶; p(0)=x(0) or y(0); p(l)=x(l) or y(l)； p(2)v二x(2) or y(2); p(3)=x(3) or y⑶; c(0)=cin; c⑴v二g(0) or (p(0) and c(0)); c(2)=g(l) or (p(l) and g(0)) or (p(l) and p(0) and c(0)); c(3)=g(2) or (p(2) and g⑴)or (p(2) and p(l) and g(0)) or (p(2) and p(l) and p(0) and c(0)); c(4)=g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(l)) or (p(3) and p(2) and p(l) and g(0)) or (p⑶ and p(2) and p(l) and p(0) and c(0)); s(0)v二x(0) xor y(0) xor c(0); s(l)=x(l) xor y(l) xor c(l); s(2)v=x(2) xor y(2) xor c(2); s(3)v=x(3) xor y(3) xor c(3); cout=c(4); end bhv; 三、实验结果 均为无延迟下测得的结果 1.全加器 2.四位串行加法器 Name VAir 100 0ns 200 Ont 3000ns 乙们 °仏 500 0ns 6C0700 0ns 800 0ns q H3 1 1 1 1 1— u^-cin 0 2 cout 1 丁 L J I Tl J ??M(3