第7章串行通信接口--DSP 山大.pptVIP

山东大学控制学院 张东亮 第7章 串行通信接口 本章内容： 7.1 SCI模块概述 7.2 SCI模块的结构 7.3 SCI的寄存器 7.4 SCI应用实例 7.5 串行外设接口SPI 7.6 增强型CAN总线eCAN 7.7 多通道缓冲串行口McBSP k=0; bReceive=0; while(1) { while(SciaRegs.SCIFFRX.bit.RXFIFST ==0) { } // 如果接受寄存器不为0则跳出 ReceivedChar = SciaRegs.SCIRXBUF.all; cBuffer[k]=ReceivedChar; if ( ReceivedChar==.) { cBuffer[k+1]=\0; nLen=k+1; bReceive=1; break; } k++; k%=16; } } } { if ( bReceive==1 ) {for ( i=0;i10;i++ ) { scia_xmit(cAnswer[i]); while(SciaRegs.SCIFFTX.bit.TXFFST !=0) { } } scia_xmit(\); for ( i=0;inLen;i++ ) { scia_xmit(cBuffer[i]); while(SciaRegs.SCIFFTX.bit.TXFFST !=0) { } } scia_xmit(\); wait(1024); for ( i=9;i16;i++ ) { scia_xmit(cString[i]); while(SciaRegs.SCIFFTX.bit.TXFFST !=0) { } } } void error(int ErrorFlag) { ErrorCount++; } // Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity void scia_loopback_init() { // Note: Clocks were turned on to the SCIA peripheral // in the InitSysCtrl() function SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback ,No parity,8 char bits, // async mode, idle-line protocol SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, // Disable RX ERR, SLEEP, TXWAKE SciaRegs.SCICTL2.all =0x0003; SciaRegs.SCICTL2.bit.TXINTENA =1; SciaRegs.SCICTL2.bit.RXBKINTENA =1; SciaRegs.SCIHBAUD =0x0001; SciaRegs.SCILBAUD =0x00e7; //波特率 9600bps SciaRegs.SCICCR.bit.LOOPBKENA =0; // disable loop back SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset } // void scia_xmit(int a) //由SCI发送一个字符a { SciaRegs.SCITXBUF=a; } // void scia_fifo_init() //初始化SCI FIFO { SciaRegs.SCIFFTX.all=0xE040; SciaRegs.SCIFFRX.all=0x204f; SciaRegs.SCIFFCT.all=0x0; } void wait(int nWait) { int i,j,k