东南大学计算结构POC报告 .pdf

Computer Organization and Architecture COURSE DESIGN NAME STUDENT NUMBER COURSE Computer Organization and Architecture Course Design PROJECT A Parallel Output Controller Basing On Verilog HDL SOFTWARE PLATFORM ISE 14.1 DATE MAR.17.2014 1. Purpose (1) To design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. (2) The use of ISE software for design and simulation. 2. Tasks (1) POCis one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices). Figure 1 Printer Connection Figure shows the connecting of a printer to the system bus through the POC. (2) The communication between POC and the printer is controlled by a “handshake ” protocol illustrated in Figure . Figure 2 The handshake -timing diagram between POC and the printer The handshaking process is described as follows: When the printer is ready to receive a character, it holds RDY=1.ThePOC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “bu