数字逻辑设计及应用：Chap5 Simulation and VerilogHDL.pptVIP

课堂练习 将你姓名拼音的第1位（大写英文字母）用ASCII码表达：1个7位二进制数； 为得到的二进制数分别添加奇校验位，得到1个8位二进制数； 将得到的8位数按顺序排列，作为3输入组合逻辑的输出，写出minterm list ； 利用卡诺图化简，写出minimal sum； module prime (a,f); input [3:0] a; output f; wire [3:0] w; assign w[0]=~a[3]a[0]; assign w[1]=a[2]~a[1]a[0]; assign w[2]=~a[3]~a[2]a[1]; assign w[3]=~a[2]a[1]a[0]; assign f=w[3]|w[2]|w[1]|w[0]; endmodule Bus signal and its operations Text entry Bus signal set Bus signal set module bus (a,b,y1,y2,y3); input[7:0] a,b; output[7:0] y1,y2,y3; assign y1=a b; assign y2=a | b; assign y3=~a; endmodule Bus signal and its operations Bus signal and its operations Chapter 5 Design simulation and HDL Combinational circuit analysis Schematic entry/ Text entry and their simulations From logic circuit to truth table Combinational logic analysis From logic circuit to logic equation Combinational logic analysis From timing diagram to truth table Combinational logic analysis Simulation: Design analysis before production Aided with computer tools: Schematic entry / Text entry Design simulation Max+Plus II from Altera .com: Include : schematic entry and HDL text editor; compiler and synthesizer; waveform editor and simulator; time analyzer; programmer; EDA Tools for digital design Open the Program: Open the Graphic editor Select logic unit and connect them Name your I/O and name your design Set up a project and select the device Name and save your design; file/project/set project to current file！ Assign /device: FLEX10K/AUTO; Check and compile your design; Design check and compile Design check and compile If compile was not success, the error information can be found in message window, we can perfect the design according to these message; If compile success, design results can be found in .rpt file. Report for design results Verify the design with input and output Waveform editor and Simulation Open the waveform editor； Click the Name area, click the List to select the ports; File/En