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Register Renaming example Register renaming R3b:=R3a + R5a (I1) R4b:=R3b + 1 (I2) R3c:=R5a + 1 (I3) R7b:=R3c + R4b (I4) Without subscript refers to logical register in instruction With subscript is hardware register allocated Note R3a R3b R3c 第三十页，共五十页。 Machine Parallelism Three hardware techniques Duplication of Resources Out of order issue Renaming Figure 13.5 shows simulation results Not worth duplication functions without register renaming Register renaming eliminates antidependencies and output dependencies Need instruction window large enough (more than 8) 第三十一页，共五十页。 Branch Prediction 80486 fetches both next sequential instruction after branch and branch target instruction Gives two cycle delay if branch taken 第三十二页，共五十页。 RISC - Delayed Branch Calculate result of branch before unusable instructions pre-fetched Always execute single instruction immediately following branch Keeps pipeline full while fetching new instruction stream Not as good for superscalar Multiple instructions need to execute in delay slot Instruction dependence problems Revert to branch prediction 第三十三页，共五十页。 Superscalar Execution 第三十四页，共五十页。 Superscalar Implementation Simultaneously fetch multiple instructions Logic to determine true dependencies involving register values Mechanisms to communicate these values Mechanisms to initiate multiple instructions in parallel Resources for parallel execution of multiple instructions Mechanisms for committing process state in correct order 第三十五页，共五十页。 Pentium 4 80486 - CISC Pentium – some superscalar components Two separate integer execution units Pentium Pro – Full blown superscalar Subsequent models refine enhance superscalar design 第三十六页，共五十页。 Pentium 4 Block Diagram 第三十七页，共五十页。 Pentium 4 Operation Fetch instructions form memory in order of static program Translate instruction into one or more fixed length RISC instructions (micro-operations) Execute micro-ops on superscalar pipeline micro-ops may be executed out of order