集成电路设计基础 课后答案.pdfVIP

1、答：确定系统规范；系统框架设计；源代码设计；FPGA综合和硬件验证；ASIC逻辑综合；综合后仿 真；版图设计；版图后仿真；提交版图数据、制版流片和芯片测试。其中所涉及的问题有对系统划分为 若干子模块并设计控制器以控制协调各子模块的工作。将行为级或寄存器级描述转换成相应门级网表 等。 √ 9、答：单进程状态机之寄存器的VHDL程序： library ieee; use ieee.std-logic-1 164.all; √ entity controller is √ port (ready: in std-logic; clk: in std-logic; read-write: in std-logic; we,oe: out std-logic); end controller; √ architecture state-machine of controller is type state-type is (idle,decision,read,write); signal present-state,next-state :state-type; begin process1; process(clk) begin if(clkevent and clk=1)then present_state=next_state; end if; end process; √ process2: process(present_state,ready,read_write) begin case present_state is when idle=we=0;oe=0; if(ready=1)then next_state=decision; end if; √ when decision=we=0;oe=0; if(read_write=1)then next_state=read; else next_state=write; end if; √ when read=we=0;oe=1; if(ready=1)then next_state=idle; else next_state=read; end if; √ when write=we=1;oe=0; if(ready=1)then next_state=idle; else next_state=write; end if; √ end case; end process; end state_machine;√ 对于这个状态机来说其双进程的VHDL程序如下： library ieee; use ieee.std-logic-1 164.all; entity controller is port (ready: in std-logic; clk: in std-logic; read-write: in std-logic; we,oe: out std-logic); end controller; architecture state-machine of controller is type state-type is (idle,decision,read,write); signal present-state,next-state :state-type; begin --process1: process(present_state,ready,read_write) begin case present_state is when idle=we=0;oe=0; if(ready=1)then next_state=decision; end if; when decision=we=0;oe=0; if(read_write=1)then next_state=read; else next_state=write; end if; when read=we=0;oe=1; if(ready=1)then next_state=idle; else next_state=read; end if; when write=we=1;oe=0; if(ready=1)then next_state=idle; else next_state=write; end if; end case; end process; --process2; process(clk) begin if(clkevent and clk=1)then present_state=next_