水上水下施工作业通航安全.pptxVIP

水上水下施工作业通航安全第1页/共32页 MotivationSignaling speeds continue to increase while interconnects change incrementally. 4-Layers boards with FR4 still rule.Solution spaces cannot shrink indefinitely.Board and silicon timings must continue to scale together.For example: The spec for PCIe Gen1 allocates 65 ps to the channel (1/3 of 2.5 GT/s timing budget).Without scaling, interconnects will take 2/3 of the Gen2 5 GT/s timing budget.We use equalization to improve timing margins.第2页/共32页 IntroductionSystems with equalization are best viewed as communications links where each block filters the signal. The s