VHDL二十四进制计数器.docxVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin is port( clk40M: in std_logic; clk1hz,clk1000hz: out std_logic ); end fenpin; architecture one of fenpin is signal a: integer range 0 to 19999 :=0; signal clk1000,clk1: std_logic; begin process(clk40M) begin if rising_edge(clk40M) then if a=19999 then clk1000=not clk1000; a=0; else a=a+1; end if ; end if; end process; clk1000hz=clk1000; process(clk1000) variable a1: integer range 0 to 499 :=0; begin if rising_edge(clk1000) then if a1=499 then clk1=not clk1;a1:=0; else a1:=a1+1; end if;end if; end process; clk1hz=clk1; end one; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port( clk1hz: in std_logic; mg,ms: buffer std_logic_vector(3 downto 0) ); end cnt10; architecture two of cnt10 is signal jw: std_logic; signal mg1,ms1,mg2,ms2: std_logic_vector(3 downto 0); signal q1,q2,q3,q4,q5,q6: std_logic_vector(3 downto 0):=0000; begin process(clk1hz) begin q5=q3; if q5=0000 then q5=0001 ;q1=0000; elsif rising_edge(clk1hz) then if q1=1001 then jw=1;q1=0000; else q1=q1+1;jw=0; end if; end if; end process; mg1=q1; process(jw) begin q6=q4; if q6=0000 then q6=0001 ;q2=0000; elsif rising_edge(jw) then q2=q2+1; end if; end process; ms1=q2; process(mg1,ms1) begin mg2=mg1;ms2=ms1; if mg2=0100 and ms2=0010 then mg2=0000;ms2=0000;q3=0000;q4=0000; else end if; end process;  mg2=mg1;ms2=ms1;q3=0001;q4=0001; mg=mg2;ms=ms2; end two; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decode is port( clk1000hz: in std_logic; mg,ms: in std_logic_vector(3 downto 0); atog: out std_logic_vector(6 downto 0); sel: out std_logic_vector(1 downto 0) ); end decode; architecture four of decode is signal q: std_logic_vector(0 to 3) ; signal count : integer range 0 to 1:=0; begin process(clk1000hz) begin if rising_edge(clk1000hz) then count=count+1; end if; end process; process(count,mg,ms) begin if count=0 then q=mg;sel=01; elsif count=