4位加法器设计EDA实验.docVIP

加法电路实验报告 实验任务 1、建立新的工程，编写四位加法器的VHDL代码。 2、编译、仿真并下载到DE2实验板测试，完成4位加法器的设计。 实验内容 1、4位串行进位加法器 1）设计电路 2）VHDL代码（设计中，先编写1位的加法，在此基础上构造4位加法） 1位全加： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT (a,b,c0:IN STD_LOGIC; s,c1:OUT STD_LOGIC); END ENTITY f_adder; ARCHITECTURE one OF f_adder IS SIGNAL abc:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN abc=abc0; PROCESS (abc) BEGIN CASE abc IS WHEN 000 = S=0 ; c1=0; WHEN 001 = S=1 ; c1=0; WHEN 010 = S=1 ; c1=0; WHEN 011 = S=0 ; c1=1; WHEN 100 = S=1 ; c1=0; WHEN 101 = S=0 ; c1=1; WHEN 110 = S=0 ; c1=1; WHEN 111 = S=1 ; c1=1; WHEN OTHERS = NULL; END CASE; END PROCESS; END ARCHITECTURE one; 4位加法： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_4adder IS PORT ( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cin : IN STD_LOGIC; cout : OUT STD_LOGIC ); END ENTITY f_4adder; ARCHITECTURE one OF f_4adder IS COMPONENT f_adder PORT( a, b,c0 : IN STD_LOGIC; c1, s : OUT STD_LOGIC ); END COMPONENT; SIGNAL c2,c3,c4 : STD_LOGIC; BEGIN u1 : f_adder PORT MAP(a = A(0),b = B(0),c0 = cin,c1 = c2,s=S(0)); u2 : f_adder PORT MAP(a = A(1),b = B(1),c0 = c2,c1 = c3,s=S(1)); u3 : f_adder PORT MAP(a = A(2),b = B(2),c0 = c3,c1 = c4,s=S(2)); u4 : f_adder PORT MAP(a = A(3),b = B(3),c0 = c4,c1 = cout,s=S(3)); END ARCHITECTURE one; 2、输入输出带锁存的4位加法器 1）设计电路 2）VHDL代码 1位锁存器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY rs IS PORT ( clk : IN BIT; r : IN STD_LOGIC; q : OUT STD_LOGIC ); END ENTITY rs; ARCHITECTURE fh1 OF rs IS BEGIN PROCESS(clk) BEGIN IF clkEVENT AND clk = 1 THEN q = r; END IF; END PROCESS; END ARCHITECTURE fh1; 4位锁存器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY rs_4 IS PORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLK0 : IN BIT ); END ENTITY rs_4; ARCHITECTURE one OF rs_4 IS COMPONENT rs PORT( clk : IN BIT; r : IN STD_LOGIC;