基于大西瓜Logic3 FP开发板序列检测器代码实现.pdfVIP

//synopsystranslate_off

`timescale10ns/1ps

//synopsystranslate_on

modulexulie_top_vlg_tst();

//constants

//generalpurposeregisters

//testvectorinputregisters

regclk;

regreset_n;

reg[7:0]xulie_data;

//wires

wire[3:0]AB;

wire[7:0]duan;

wire[3:0]wei;

//assignstatements(ifany)

////例化顶层模块

xulie_topi1(

//portmap-connectionweenmasterportsandsignals/registers

.clk(clk),

.reset_n(reset_n),

.AB(AB),

.wei(wei),

.duan(duan),

.xulie_data(xulie_data)

);

initial

begin

//codethatexecutesonlyonce

//insertcodehere--begin

//初始化设置信号

clk=1b0;

reset_n=1b0;

xulie_data=8//设置要检测出的序列值

//--end

$disy(Runningtestbench);

end

always

//optionalsensitivitylist

//@(event1orevent2oreventn)

begin