OTUF design培训教材电子互联.pptVIP

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  • 2026-05-28 发布于浙江
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OTUF(2.5G)PLLDesignInthisapplicationtherearetwolineclockjittercleanupPLLs(EastandWest)TheEastjittercleanupPLLrunsateither155.52MHzor166.67MHz(FECmode).InthisdesignITU-TG.783jittertolerance,jittertransfer,andjittergenerationspecificationsmustbemet.ThejittercleanupPLLsetsthejittertransferandplaysapartinjittergeneration(theMUXCMUisthemajorsourceofTXjitter).TheDEMUXCDRdeterminesjittertolerance.

PrototypePLLDesignTheinitialPLLdesignisdonewithanidealPLLmodelbasedontheblockdiagramshownhere.ThePLLphasedete

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