《VerilogHDL负责数字电路设计（AI助学版）》课件 10 - 2 函数 .pptxVIP

10.2函数;moduleparity;//偶效验位的计算

...

reg[31:0]addr;

regparity;

always@(addr)

begin

parity=calc_parity(addr);

$display(Paritycalculated=%b,calc_parity(addr));

end

...

functioncalc_parity;

input[31:0]address;

begin

calc_parity=^address;

end

endfunction

...

...

endmodule

;functioncalc_parity(input[31:0]address);

begin

calc_parity=^address;

end

endfunction;moduleshifter;

`defineLEFT_SHIFT1b0

`defineRIGHT_SHIFT1b1

reg[31:0]addr,left_addr,right_addr;

regcontrol;

always@(addr)

begin

left_addr=sh