Embedding of Asynchronous Wave Pipelines into Synchronous Data异步波向同步数据的嵌入.pptVIP

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Embedding of Asynchronous Wave Pipelines into Synchronous Data异步波向同步数据的嵌入.ppt

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Embedding of Asynchronous Wave Pipelines into Synchronous Data异步波向同步数据的嵌入

3. Mai 1999 Embedding of Asynchronous Wave Pipelines into Synchronous Data Processing Some Notations... Asynchronous Wave Pipeline (AWP) Circuits Logic style used has to minimize delay variation Earlier work focused on bipolar logic (ECL, CML), but CMOS is mainstream Static CMOS is not well suited for wave piping, fixing the problem results in more power and slower speed Pass transistor logic gives slopy edges thereby introducing delay variation Dynamic logic is attractive as only output high transition is data-dependant, output pulldown is done by precharge What is needed is a dynamic logic family without precharge overhead: SRCMOS SRCMOS Distinguishing property of our SRCMOS circuits: precharge feedback is fully local, and NMOS trees are delay balanced Generic Synchronous Pipeline * Stephan Hermanns, Sorin Alexander Huss University of Technology Darmstadt, Germany Wave Logic Wave Latch Wave Latch Data req_in req_out matched delay More than one data and request propagating coherently One-sided cycle time constraint Delay must track logic over PTV corners N inputs output Logic Latch/Reg Latch/Reg Data Clk Static ? Pulse Conversion: Transistor Level Data input has to be stable during evaluation time teval after rising edge ofclka or clkb Pulse width is defined by feedback path of SRCMOS Generates pulse according to data input after rising edge of clka or clkb Pulse ? Static Conversion: Schematic Level Data pulse is catched asynchronous and output statically in synchronization with request pulse Pulse ? Static Conversion: Transistor Level Request Generation: Register is omitted Input to Register is stable in [M?Tclk-tsetup,M?Tclk+thold] This has to be sufficient to Pulse Generator to evaluate Input Data Hold time thold is crucial ? Further Investigation Request Generation: Register is kept Only non-inverting outputs used to form clock-like Signal to Pulse-Gen. ? no Skew Request and Data Pulses are generated uniformly No additionally Reset of Register needed Dela