Clock Skew.pdf

/users/kia/Courses/EE5324 VLSI Design II – ? Kia Bazargan Spring 2006 EE 5324 - VLSI Design II - ? Kia Bazargan 332 EE 5324 – VLSI Design II Kia Bazargan University of Minnesota Part VIII: Timing Issues Spring 2006 EE 5324 - VLSI Design II - ? Kia Bazargan 333 References and Copyright ? Textbooks referenced [Rab96] J. M. Rabaey “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 1996. ? Slides used(Modified by Kia when necessary) [?Prentice Hall] ? Prentice Hall 1995, ? UCB 1996 Slides for [Rab96] /Classes/IcBook/instructors.html Spring 2006 EE 5324 - VLSI Design II - ? Kia Bazargan 334 Why Deal With Timing? ? Clock Makes sure signals are settled before being written Controls the order of operations ? Problem? Physical implementation of the circuit ≠ what we planned Why? o Wires incur delay on signals o Clock edge might arrive too early or too late ? Challenges Clock routing Synchronization protocols /users/kia/Courses/EE5324 VLSI Design II – ? Kia Bazargan Spring 2006 EE 5324 - VLSI Design II - ? Kia Bazargan 335 Clock Skew ? Clock signal Connects to all registers/flip-flops Connects to all pre-charge/evaluate of dynamic logic Huge fanout large capacitive load Routed to all parts of the chip Huge capacitance of the clock net itself Example: Alpha μprocessor: 3.24 nF (40% chip C) ? Clock skew Clock net has huge RC Signal arrival time depends on the length of the dest from source Not the “same” clock signal for different destinations ? Why important? Timing violated Larger chips even worse Spring 2006 EE 5324 - VLSI Design II - ? Kia Bazargan 336 Clock Wire Delay CL r c Rs r = 0.07 Ω/l c=0.04 fF/μm2 (Tungsten wire) [?Prentice Hall] Spring 2006 EE 5324 - VLSI Design II - ? Kia Bazargan 337 Reference Circuit: Pipelined Datapath ? We use this circuit to analyze the problem CL1 R1 CL2 R2 CL3 R3 tφ’ tφ’’ tφ’’’ φ In Outti tl,min tl,max tr,min tr,max Skew: δ = tφ’’ – tφ’ /users/kia/Courses/EE5324 VLSI Design II – ? Kia Bazargan Spring 2006 EE 5324 - VLSI