COA课件15讲稿.ppt

William Stallings Computer Organization and Architecture6th Edition Chapter 16 Control Unit Operation 控制器的操作 ※§16.1 Micro-Operations 微操作 A computer executes a program Fetch/execute cycle Each cycle has a number of steps see chapter 12 pipelining Called micro-operations —μOPs information flow Each step does very little Atomic(基本的或原子的) operation of CPU Constituent Elements of Program Execution 4 Registers Four registers are essential to instruction execution： Memory Address Register (MAR) Connected to address bus Specifies address for read or write op Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) Holds last instruction fetched Fetch Sequence (symbolic) t1: (PC) - MAR t2: (MAR) Memory by address bus read Memory by control bus t3: Memory MBR by data bus t4: (MBR) - IR (PC) +1 - PC (Maybe happen in t2,t3 and t4) Rules for Clock Cycle Grouping Proper sequence must be followed MAR - (PC) must precede MBR - Memory Conflicts must be avoided Must not read write same register at same time MBR - Memory IR - (MBR) must not be in same cycle Also: PC - (PC) +1 involves addition Use ALU May need additional micro-operations Indirect Cycle (symbolic) t1: Ad(MBR) - MAR t2: (MAR) - Memory read - Memory t3： Memory - MBR Ad(MBR) — address field of MBR (at last MBR contains an address of operand) Execute Cycle Micro-operations in fetch, indirect, and interrupt cycle is simple and predictable But in execute cycle ,it is related with opcode of instruction. Different for each instruction Execute Cycle(ADD) e.g. ADD R1,X; (R1)+(X) -R1 — add the contents of location X to Register 1 , result in R1 Execute Cycle (ADD) ADD R1,X; (R1)+(X) - R1 —t1: Ad(MBR) - MAR —t2: (MAR) - Memory read -Memory —t3: Memory-