电子EDA复习资料（五邑大学）EDA实验编程.docVIP

实验三、数字频率计 4位数字频率计控制模块 module fre_pm1(clk,rst,count_en,count_clr,load); input clk,rst;output count_en,count_clr,load;reg count_en,load; always @(posedge clk) begin if(rst) begin count_en=0;load=1;end else begin count_en=~count_en; load=~count_en; end end assign count_clr=~clkload; endmodule 四位频率计计数子模块 module a1(out,cout,en,clr,clk); input en,clr,clk;output[3:0] out;output cout;reg[3:0] out; always @(posedge clk or posedge clr) begin if(clr) out=0; else if(en) begin if(out==9) out=0;else out=out+1;end end assign cout=((out==9)en)?1:0; endmodule 十六位锁存器模块 module b1(qo,din,load); input load;input[15:0] din;output[15:0] qo;reg[15:0] qo; always @(posedge load) begin qo=din;end endmodule    实验四 英文之母显示电路 module abcd(clr,clk,a,b,c,d,e,f,g,w); input clr,clk; output a,b,c,d,e,f,g,w; reg[3:0] out; reg a,b,c,d,e,f,g,w; always @(posedge clk or posedge clr) begin if(clr) out=0; else begin if(out==15) out=0; else out=out+1; end end always @(out) begin case(out) 4h0:{a,b,c,d,e,f,g}=7b1111110; 4h1:{a,b,c,d,e,f,g}=7b0110000; 4h2:{a,b,c,d,e,f,g}=7b1101101; 4h3:{a,b,c,d,e,f,g}=7b1111001; 4h4:{a,b,c,d,e,f,g}=7b0110011; 4h5:{a,b,c,d,e,f,g}=7b1011011; 4h6:{a,b,c,d,e,f,g}=7b1011111; 4h7:{a,b,c,d,e,f,g}=7b1110000; 4h8:{a,b,c,d,e,f,g}=7b1111111; 4h9:{a,b,c,d,e,f,g}=7b1110011; 4ha:{a,b,c,d,e,f,g}=7b1110111; 4hb:{a,b,c,d,e,f,g}=7b0011111; 4hc:{a,b,c,d,e,f,g}=7b1001110; 4hd:{a,b,c,d,e,f,g}=7b0111101; 4he:{a,b,c,d,e,f,g}=7b1001111; 4hf:{a,b,c,d,e,f,g}=7b1000111; default:{a,b,c,d,e,f,g}=7b0000001; endcase w=1; end endmodule  实验五 序列检测器 module lychy(x,z,clk,reset,state); input x,clk,reset;output z;output[3:0]state; reg[3:0]state;reg z; parameter s0=b000,s1=b001,s2=b010,s3=b011,s4=b100,s5=b101,s6=b110,s7=b111; always @(posedge clk) begin if(reset) begin state=s0;z=0;end else casex(state) s0: begin if(x==0) begin state=s0;z=0;end else begin state=s1;z=0;end end s1: begin if(x==0) begin state=s0;z=0;end else begin st