VHDL与数字集成电路设计VHDL1-2.pptVIP

* * * 1.1 程序的结构 library、entity、port 1.2 设计的表达 architecture、signal 1.3 结构表达与运算表达 1.4 数字系统的进程表达 process 第一章 VHDL对电路设计的基本描述 VHDL与数字集成电路设计 VHDL的构造体：architecture 1.2 设计的表达 architecture、signal 实体与构造体的关系 1.2 设计的表达 architecture、signal USE WORK.std_logic_1164.ALL; ENTITY decode IS PORT( a, b, en : IN std_logic; q0, q1, q2, q3 : OUT std_logic); END decode; 实体与构造体的关系 1.2 设计的表达 architecture、signal ARCHITECTURE structural OF decode IS COMPONENT inv PORT( a: IN std_logic; b: OUT std_logic); END COMPONENT; COMPONENT and3 PORT( a1, a2, a3 : IN std_logic; o1 : OUT std_logic); END COMPONENT; SIGNAL nota,notb : std_logic; BEGIN I1 : inv PORT MAP(a, nota); I2 : inv PORT MAP(b, notb); A1 : and3 PORT MAP(nota, en, notb, Q0); A2 : and3 PORT MAP(a, en, notb, Q1); A3 : and3 PORT MAP(nota, en, b, Q2); A4 : and3 PORT MAP(a, en, b, Q3); END structural; 1.2 设计的表达 architecture、signal 低级配置：对解码器实体低级形式的元件配置如下： CONFIGURATION decode_llcon OF decode IS FOR structural FOR I1 : inv USE CONFIGURATION WORK.invcon(behav); END FOR; FOR I2 : inv USE CONFIGURATION WORK.invcon(behav);; END FOR; FOR ALL : and3 USE CONFIGURATION WORK.and3con(behav); END FOR; END structural; END decode_llcon; 实体与构造体的关系 1.2 设计的表达 architecture、signal USE WORK.std_logic_1164.ALL; ENTITY inv IS PORT( a : IN std_logic; b : OUT std_logic); END inv; ARCHITECTURE behave OF inv IS BEGIN b = NOT(a) AFTER 5 ns; END behave; CONFIGURATION invcon OF inv IS FOR behave END FOR; END invcon; 实体与构造体的关系 1.2 设计的表达 architecture、signal USE WORK.std_logic_1164.ALL; ENTITY and3 IS PORT( a1, a2, a3 : IN std_logic; o1 : OUT std_logic); END and3; ARCHITECTURE behave OF and3 IS BEGIN o1 = a1 AND a2 AND a3 AFTER 5 ns; END behave; CONFIGURATION and3con OF and3 IS FOR behave END FOR; END and3con; 1.2 设计的表达 architecture、signal USE WORK.std_logic_1164.ALL; ENTITY counter IS PORT(load, cle