synopsys学习资料-minpower_overview.pdf

DesignWare minPower Components Overview DesignWare minPower Components Library Low-Power Overview DesignWare minPower Component 1.1 Introduction The Low Power (low-power) components populate a library that implements techniques to produce power saving circuits in high-performance designs. The main features that can be enabled to minimize power consumption when using the Low Power Library components are as follows: ❖ Maximize clock gate insertion structures within components ❖ Pipeline management of pipelined components ❖ Datapath gating for components with enable control 1.2 Power Savings via Clock Gate Insertion All low-power sequential and pipelined DesignWare components (DW__pipe and DW_lp_piped_) are coded in such a way to allow clock gate insertion by Power Compiler. To enable this feature for DesignWare components, the Power Compiler variable power_cg_designware must be set to true during synthesis setup. Example: set power_cg_designware true # tcl syntax 1.3 Pipeline Control Provides Power Savings (and enables Clock Gating) In general, DW_lp_piped_ components contain a pipeline control block than runs in parallel to the pipeline register levels that monitors the activity through the pipeline (see Figure 1-1 block diagram for pre- register retiming depiction). In cases where there is inactivity on a particular register level of the pipeline, the pipeline control disables those levels to promote power savings. Furthermore, if using the Synopsys Power Compiler tool, the presence of the pipeline control and its wiring to the pipeline register levels provides an opportunity for increased power reduction in the form of clock gating (by setting