Altera的几个常用的Synthesisattributes.docVIP

各厂商综合工具，对HDL综合时都定义了一些综合属性这些属性可指定a declaration,a module item,a statement, or a port connection 不同的综合方式。 语法为： /* synthesis, any_company_specific_attribute = value_or_optional_value */ 下面就是Altera的几个常用的Synthesis attributes Noprune A Verilog HDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin. For example: reg reg1 /* synthesis noprune */; keep A Verilog HDL synthesis attribute that directs Analysis Synthesis to not minimize or remove a particular net when optimizing combinational logic. For example: wire keep_wire /* synthesis keep */; preserve A Verilog HDL synthesis attribute that directs Analysis Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers. For example: reg reg1 /* synthesis preserve */; ram_init_file A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory. For example: reg [7:0] mem[0:255] /* synthesis ram_init_file = my_init_file.mif */; ramstyle A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM. M512, M4K, M9K, M144K, MLAB, M-RAM” For example: reg [0:7] my_ram[0:63] /* synthesis ramstyle = M512 */; translate_off or translate_on Verilog HDL synthesis directives that direct Analysis Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis. For example: parameter tpd = 2; // Generic delays // synthesis translate_off #tpd; // synthesis translate_on 关于状态机有下面三个综合属性: full_caseA Verilog HDL synthesis attribute that directs Analysis Synthesis to treat unspecified state values in a Verilog Design File Case Statement as dont care values, and therefore to treat the Case Statement as full. 仅用于Verilog ,与case 语句一起使用表明所有可能的状态都已经给出不需要其他逻辑保持信号的值. module full_case (a, sel, y);?? input [3:0] a;?? input [1:0] sel;?? o