virtex6 fpga architecture_房文雅.ppt

Virtex-6 FPGA Introduction Virtex-6 LXT FPGA General logic + serial Virtex-6 SXT FPGA Rich DSP and block RAM + serial Virtex-6 HXT FPGA Highest bandwidth serial针对各种需要最高的串行连接能力，多达64个串行收发器，以及可支持高达11.2Gbps带宽的通信应用而优化。 Note that a hard processor core is NOT available in any of the Spartan-6 orVirtex-6 devices. Architecture Power Savings More direct routing Less capacitance LUT6 architecture Less power than LUT4 Global CEs Reduces dynamic power Hardened IP reduces power consumption versus a LUT implementation—Gigabit Transceivers, PCI Express? technology, EMAC，DSP, block RAM / FIFO Architecture Alignment Virtex-6 LXT / SXT FPGA Highlights 74K to 760K logic cells 5 Mbits to 38 Mbits of Block RAM Memory-rich architecture Up to 2,000 DSP slices Up to 1,200 SelectIO. interface pins Low-latency memory and parallel interfacing Up to 36 6.5-Gbps serial transceivers，225-Gbps aggregate serial bandwidth in a single device Hardened, full-featured PCI Express technology 10/100/1000 Mbps Ethernet MACs Easy, high-performance protocol support that saves programmable logic Advanced packaging with superior signal integrity Virtex-6 FPGA Logic Fabric Virtex-6 FPGA Configurable Logic Block (CLB) Each CLB contains two slices Each slice contains four 6-input Lookup Tables (6LUT) Slices implement logic functions (slice_L) Slices for memories and shift registers (slice_M) LUT6 implements: All functions of up to six variables Two functions of up to five or fewer variables each Shift registers up to 32 stages long Memories of 64 bits Multiple configurations within a slice FPGA Slice Resources Four six-input Look Up Tables (LUT) Wide multiplexers Carry chain, This is supported on four of the eight flip-flops: Four flip-flop/latches Four additional flip-flops -These are the new flip-flops The implementation tools (MAP) may affect the packing of the design Wide Multiplexers Each F7MUX combines the outputs of two LUTs together -Can implement an arbitrary 7-input fu