基于FPGA 的No.7 信令FISU 过滤.pdfVIP

36 6 2010 3 Vol.36 No.6 Computer Engineering March 2010 ·· 2010 A TP393 FPGA No.7 FISU ( 400030) CPU (FISU)No.7 FISU FPGA FISU FPGA CPU ISE ModelSim No.7 No.7 Signaling FISU Filter Based on FPGA LUO Ming-yang, LIAO Hong-yun, SU Ling-xu (Chongqing Jinmei Communication Co., Ltd., Chongqing 400030) AbstractIn allusion to the disadvantage of processing Fill-in Signal Unit(FISU) using CPU, on the basis of analyzing the process of initial aligning and FISU processing in No.7 signaling system, a new design scheme adopting Field-Programmable Gate Array(FPGA) to achieve FISU filter is put forward. The principle figures, communication mechanism between FPGA and CPU, and signal processing flow charts are carried out. ISE and ModelSim software are used to achieve simulation. Simulation result proves that the scheme is correct, feasible and effective. Key wordsNo.7 signaling system; process of initial aligning; Fill-in Signal Unit(FISU) filter; Field-Programmable Gate Array(FPGA) 1 / (Backward Indicator Bit/Backward Sequence No.7 Number, BIB/BSN)[2] E1 TS16 (2) LSSU MSU [1] CPU FIB/FSN BIB/BSN (High-level Data Link Controller, HDLC) No.7 FIB/FSN BIB/BSN FISU [2] (3)FIFO CPU (Fill-in Signal Unit, FISU) No.7 CPU (4)CPU 100 () (5)CPU CPU 95% (6)HDLC HDLC