Dynamic Scheduling - Abandah动态调度abandah.pptVIP

* CPE 731, ILP3 * Why can Tomasulo overlap iterations of loops? Register renaming Multiple iterations use different physical destinations for registers (dynamic loop unrolling). Reservation stations Permit instruction issue to advance past integer control flow operations Also buffer old values of registers - totally avoiding the WAR stall Other perspective: Tomasulo building data flow dependency graph on the fly * CPE 731, ILP3 * Tomasulo’s scheme offers 2 major advantages Distribution of the hazard detection logic distributed reservation stations and the CDB If multiple instructions waiting on single result, each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB If a centralized register file were used, the units would have to read their results from the registers when register buses are available Elimination of stalls for WAW and WAR hazards * CPE 731, ILP3 * Tomasulo Drawbacks Complexity delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 in CA:AQA 2/e, but not in silicon! Many associative stores (CDB) at high speed Performance limited by Common Data Bus Each CDB must go to multiple functional units ?high capacitance, high wiring density Number of functional units that can complete per cycle limited to one! Multiple CDBs ? more FU logic for parallel assoc stores Non-precise interrupts! We will address this later * CPE 731, ILP3 * And In Conclusion … #1 Dynamic HW exploiting ILP Works when can’t know dependence at compile time Can hide L1 cache misses Code for one machine runs well on another * CPE 731, ILP3 * And In Conclusion … #2 Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Helps cache misses as well Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants