时间交替adc系统实现-集成电路工程专业论文.docxVIP

摘要随着现代通信技术的发展，特别是超宽带通信系统的发展以及软件无线电概念的提出， 实时通信系统对数据采集系统的速度和精度要求越来越高。在目前集成电路工艺水平下，单 片 ADC 的采样速度和转换精度不可能同时提高。为了在不牺牲精度的前提下提高采样率，时 间交替采样系统被提出。在时间交替采样系统里有 M 片 ADC，这些 ADC 的采样时钟相互之 间相位差为 360/M 度。系统里这些 ADC 是同时工作，因此对于被采样信号来说，时间交替 采样系统的采样率是单片 ADC 的 M 倍，理论上系统的精度还保持单片 ADC 的精度。文章围绕时间交替 ADC 系统硬件电路制作展开，详细阐述了基于三片 AD9480 的时间交 替 ADC 系统的各部分电路。首先介绍了采样定理，指出采样率提高的重要性，紧接着介绍时 间交替采样的原理以及采样时钟的偏斜和抖动对采样的影响。然后分别介绍了时间交替 ADC 系统中交替时间采样时钟产生电路、差分放大器的放大电路、电源系统的设计、高速数据缓 存电路等的设计，同时在电路设计的关键点给出说明或者仿真结果。由于 PCB 电路板制作好 坏直接关系到高速数据的正确传输，本文专门用一章讲解信号完整性相关的知识以及其在电 路设计中的指导作用，同时针对本系统的差分信号特别介绍了差分信号的阻抗匹配方式。最后根据实际制作的电路板测试各个部分电路的性能，并给出最后的结果。关键词：时间交替采样，信号完整性，高速数据缓存，高速 PCB 设计，时钟分配ABSTRACTWith the development of modern communication technology, particularly the development of ultra-wide band communication system as well as the concept of software radio proposed, real-time communication system offers an increasing demand on increasing the speed and accuracy of the data acquisition system. In the current level of integrated circuit production processing, the monolithic ADC sampling rate and conversion accuracy can not be increased simultaneously. In order to increase the sampling rate without sacrificing the accuracy, time-interleaved sampling system has been brought forward. There are M pieces of ADC in time-interleaved sampling system. These ADC sampling clocks have 360/M degrees phase difference between each other. In time-interleaved sampling system, all the ADCs are working. So for the sampled signal, the sample rate of time-interleaved ADC system is M times larger than that of monolithic ADC. And theoretically the accuracy of the system is also maintained the monolithic ADCs precision.This paper focuses on the time-interleaved ADC system circuit design and elaborats each part of the system, which contains three AD9480 ADC converters. At first, the sampling theorem is introduced, and the importance of high-speed sampling rate is pointed out. After that, the principle of time-interleaved sampling is explanded and the af