光刻机工件台与掩模台同步控制分析-analysis of synchronous control between workpiece stage and mask stage of lithography machine.docxVIP

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光刻机工件台与掩模台同步控制分析-analysis of synchronous control between workpiece stage and mask stage of lithography machine.docx

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光刻机工件台与掩模台同步控制分析-analysis of synchronous control between workpiece stage and mask stage of lithography machine

哈尔哈尔滨工业大学工学硕士学位论文IIIIAbstractStepscan lithography is the current mainstream integrated circuit manufacturing equipment. Its development involves optical, mechanical, precision measurement, control, so it is one of the most sophisticated equipments which manufacturing integrated circuits. Synchronization control for wafer stage and reticle stage needs by the technological development of lithography machine, and synchronization controlperformance directly affects lithography resolution and overlay accuracy， is a keytechnology of stepscan lithography.In this paper, considering synchronization control problem, from synchronization control strategy and synchronization control algorithm, first analyzing the characteristics of the cross-coupling and master-slave synchronization control strategy and synchronization control strategy adopted by ASML company. considering repeat- able action of the scanning exposure process, designing iterative learning control law for synchronization control algorithm, and theoretically proving the convergence of iterative learning law.Synchronization control card is one of the core control boards of stepscan lithography, high-performance synchronization control card is nessesary to achieve high speed processing and high-precision synchronization control. Therefore using high-performance DSP and FPGA as the core device of synchronization control card, DSP with TIs TMS320C6414 the central processor, can achieve high-speed data processing operations, FPGA using Alteras EP2S60F1020 access chips for the interface, in order to meet more kind of interface to access communication.Synchronization control card access through the FPGA for each interface, designing the appropriate interface logic modules. First planing overall block diagram of the interface logic to the FPGA dual-port RAM for the cache, connecting the interface logic module and DSP EMIF interface logic module, and then designing interface logic module by working principle, and carring