时间交织adc数字校正算法的分析与开发-analysis and development of digital correction algorithm for time interleaved adc.docxVIP
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时间交织adc数字校正算法的分析与开发-analysis and development of digital correction algorithm for time interleaved adc
摘要摘要随着IC产业的快速发展和数字技术在信号处理、存储、传输等领域的广泛运用,作为真实世界与数字世界桥梁的模数转换器(ADC)日益成为国内外相关机构的研究热点。然而,受制于集成电路设计与制造水平,单一通道ADC的性能经过一段的时期高速提升已经接近发展瓶颈。时间交织模数转换器(time-interleavedADC)使用多个子ADC同时工作,并交替输出转换结果,从而在不增加设计难度的情况下成倍提高系统的转换速率,为突破ADC性能的发展瓶颈提供了有效方法。然而,包括失调失配、增益失配和采样时钟偏移等通道间失配严重影响了时间交织ADC的性能。本文详细研究了TIADC中上述三种误差的产生、对系统性能的影响及频谱上的体现。在分析对比现有的误差校正方法之后,根据通道间失调失配、增益失配和采样时钟偏移三种非理想因素的统计规律,提出了自适应的数字后台校正算法。然后使用simulink建模与仿真验证了算法的有效性,并使用verilog硬件描述语言完成了校正系统的代码设计与仿真,最后基于55nmCMOS工艺,使用数字集成电路后端设计相关EDA工具完成了校正系统的物理综合、版图设计与优化、逻辑等效检查与时序分析、后仿真等工作。校正系统算法简单,易于实现,校正效果明显,对于工作于800MHz的2通道12bit时间交织ADC,校正后数据的SNR提升了37dB,ENOB提升了6bits。关键词:时间交织,ADC,通道间失配,数字校正,数字后端ABSTRACTABSTRACTWiththerapiddevelopmentoftheintegratedcircuitindustryandthewidespreadapplicationsofdigitaltechnologyinthefieldsofinformationprocessing,storageandtransmission,asthebridgeoftherealworldanddigitalworld,ADCsarebecomingahotresearchtopicofrelatedinstitutionsathomeandabroad.However,limitedbythequalityofintegratedcircuitdesignandmanufacturingtechnology,afteraperiodofrapidgrowth,thepoformanceofsinglechannelADCsiscomingtoabottleneck.Intime-interleavedADC,severalADCsworkparallellyandoutputtheconverteddatainsequence.Thisarchitecture,whichmultiplestheconversionratewithoutincreasingdesigndifficulty,providesanefficientwaytobreakthroughthebottleneckofADC’sdevelopment.However,thepoformanceoftime-interleavedADCsisseriouslyaffectedbyinter-channelmismatches,suchasoffsetmismatch,gainmismatchandsampleclockskew.Detailedanalysisonthecauses,impactandreflectiononfrequencyspectrumoftheseinter-channelmismatchesispresentedinthispaper.Afteranalysisandcomparisonofexistingerrorcalibrationmethodsofthemismatches,weproposedanadaptivedigitalbackgroundcalibrationmethod,basedonthestatisticalcharacteristicofthesethreekindsofnonidealfactors.WiththefeasibilityofthealgorithmverifiedbySimulink,webuiltandtestedthecalibrationarchitecturebyverilogHDLandaccomplishedthephysicalsynthesis,layoutdesignandoptimization,logicandtimingcheckandpost-simulationbydigitalICback-endEDAtools.Thecalibratio
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