超大规模集成电路的内建自测试(BIST)技术研究-电力电子与电力传动专业论文.docxVIP

摘要 摘要 -I-万方数据 -I- 万方数据 摘 要 随着超大规模集成电路（Very Large Scale Integrated circuites ，VLSI）设计和制 造技术地迅速发展，电路尺寸日益减小，复杂程度愈来愈高，VLSI 测试成为迫切 需要解决的问题，而可测性设计（Design For Testability，DFT）成为解决当前 VLSI 测试问题的主要手段，内建自测试（Built-In Self-Test，BIST）以其较高的故障故障 覆盖率和能完成自测试的优点成为一种广泛应用的 DFT 技术。近年来，边界扫描 （Boundary Scan，BS）和内建自测试相结合的测试技术也成为测试领域研究的焦点。 本文首先针对 VLSI 测试所面临的困难，依据电路分块测试的思想，研究分析 了数字集成电路的分块方法和分块电路的测试方法。在此基础上，根据内建自测试 （Built-In Self-Test）可层次化设计的特点，提出对底层的 VLSI 子块进行内建自测 试设计的方案，实现了 VLSI_BIST（Built-In Self-Test）子块中各模块的功能仿真。 最后基于边界扫描 IEEE1149.1 标准设计了 VLSI 子块级 BIST 测试架构，即 JTAG_BIST 架构，完成了 JTAG_BIST 测试接口设计和 VLSI_BIST 子块关键技术的 设计，并进行功能仿真验证，最终实现了上层测试系统通过 JTAG_BIST 测试接口 控制下层 VLSI_BIST 子块进行自测试。本文的主要工作和创新点是提出 VLSI 子块 的内建自测试设计方案，即基于边界扫描并行链的 VLSI 子块级 BIST 测试架构设 计及仿真验证。 验证结果表明 VLSI_BIST 子块能够在接收上层指令下完成自测试，而上层测试 系统能够通过 JTAG_BIST 测试接口对下层 VLSI_BSIT 子块进行自测试控制。全文 基于电路分块的思想，结合边界扫描和内建自测试技术，较好地完成了 JTAG_BIST 子块的层次化测试架构设计及仿真验证，对于 VLSI 测试技术的发展具有一定的意 义。 关键词:超大规模集成电路；电路分块；VLSI 子块；边界扫描；内建自测试 -II-万方数据 -II- 万方数据 Abstract With the rapid development of VLSI designing and manufacturing technology, the size of circuit chip shrinks and becomes more complexity, thus the test of VLSI has become a significant problem. At present, DFT(Design For Testability) has already become the main solution for testing，and BIST technology has been became a widely used DFT method with the advantages of higher fault coverage and self-test ability. Besides, a combination testing technique of boundary scan (BS) and BIST has also become a focus in the field of IC testing in recent years. At the beginning of this thesis, the partitioning method of digital integrated circuits and the method for sub-block circuit testing has been analyzed with the idea of test by sub-block, in order to solve the problem of VLSI testing. Then the BIST scheme for the bottom VLSI sub-block has been given in accordance with the characteristic of the hierarchical architecture design of BIST, and the simulation of each BIST module has also been carried out. After that, th