超高速时钟恢复电路的研究与芯片设计-微电子学与固体电子学专业论文.docxVIP

摘 摘 要 摘 摘 要 摘 要 随着信息产业的不断发展，数据速率越来越高，在传输过程中数据信号发生衰减 和失真，为了减小误码率，需要一个稳定的时钟信号来重新定时数据信号，减小抖动 和干扰。因此，时钟恢复电路是高速数据通信不可缺少的关键电路。 基于SMIC 0.18μm混合信号CMOS工艺，本文设计了一个符合STM-16标准的时钟 恢复电路。本文采用锁相环结构实现超高速时钟恢复电路。锁相环结构是三阶的电荷 泵锁相环，鉴相器采用正交鉴频鉴相器，环路滤波器采用二阶无源滤波器，压控振荡 器采用电感电容压控振荡器，电荷泵采用加法器电路。正交鉴频鉴相器既可以从非归 零码CNRZ)信号中提取时钟信息，至可以扩大锁相环的捕获范围。本文采用电流模 逻辑电路实现正交鉴频鉴相器、加法器和缓冲器，有利于单片集成且工作速度高。 本文给出了时钟恢复电路的基本原理以及锁相环型时钟恢复电路设计、仿真结果 和版图设计。根据STM-16的标准，划分出每个模块的性能指标，根据这些指标计算出 电路的参数。仿真结果显示本文设计的电路实现了2.5GHz时钟恢复功能，时钟恢复电 路的锁定时间为25μs，输出时钟信号抖动为2.45ps，性能符合STM-16的标准。 关键词:时钟恢复电路; 电感电容压控振荡器; 电荷泵锁相环; 正交鉴频鉴相器. 万方数据 I – – – PAGE IV – 万方数据 Abstract With the development of the information industry, data rate become higher and higher. Attenuation and distortion of data signal will appear in transmission. In order to reduce the error rate, a stable clock signal needs to re-timing data signals and reducing jitter and interference. Therefore, the clock recovery circuit(CRC)is the key part of high-speed data communications. Based on 0.18μm mix-signaled CMOS process, a clock recovery circuit for STM- 16 standard is proposed. In this thesis, a phase-locked loop architecture is employed to achieve ultra high-speed clock recovery circuit. Phase-locked loop structure is the third-order CP-PLL. Phase detector is orthogonal frequency discriminator phase de- tector. Loop filter is the second-order passive filter. Voltage-controlled oscillator is inductor capacitor voltage-controlled oscillator. Charge pump is implemented by adder circuit. The clock information is extracted from the NRZ signal by Orthogonal fre- quency discriminator phase detector. At the same time, it can expand the capture range of phase-locked loop. quadrature PFD, adders and buffers are implemented by a current-mode logic circuit.This is better to monolithic integration and high speed. In this paper, the basic principle of clock recovery circuit and the PLL-based clock recovery circuit is introduced, and the complete circuit is designed. The simulation results and