高分率cfa图像实时重构及其vga显示控制器设计-信号与信息处理专业论文.docxVIP

太原理工大学硕士研究生学位论文1024×768的图像数据。 太原理工大学硕士研究生学位论文 1024×768的图像数据。 (3)基于FPGA实现高分辨率双缓存VGA显示控制器 用VHDL语言构建双缓存VGA显示控制器，实现对输入是每像素 16bit(RGB565)、分辨率为1024x768、帧频低于20HZ的逐行图像进行 频率提升，输出图像格式是XGA@60HZ。 关键词：FPGA，CFA图像插值，显示控制器，频率提升 II 太原理工大学硕士研究生学位论文THE 太原理工大学硕士研究生学位论文 THE DESIGNING 0F REAL—T1ME RECONSTRUCTION AND VGA Dl SPLAY CONTROLLER OF HIGH RESOLUTION CFA IMAGE 19 ABSTRACT ‘ With the increase of video exhibit table image sensor resolution，the technology of real—time display movement image is becoming the kernel research task ofproduct．At present,current solution is DSP+ASIC chip，DSP implements CFA interpolation algorithm,which reconstructs Bayer template CFA image to color image，ASIC chip upgrades the low frame frequency color image of DSP processed to the standard flame frequency of VGA display interface．This paper brings forward a design scheme，which USeS FPGA substituting DSP+ASIC truss． This paper focuses on the three aspects below and achieves some results： (1)Hardware implementing ofFPGA development platform This paper adopts the XC2S300E··PQ208-·6·-C of Xilinx company as kemel device，chooses CMOS image sensor module OV9650 to be the CFA image import—source，regards two pieces of SDRAM as frame buffer memory, builds hardware development platform ofFPGA． (2)Using VHDL language implements real-time bilinear interpolation algorithm lII 太原理r大学硕十研究生学位论文By 太原理r大学硕十研究生学位论文 By analyzing CFA image interpolation algorithm，implements real—time bilinear interpolation algorithm based on FPGA，for the import CFA Bayer template image data of 8bit per-pixel at 1 024x768，completes real-time reconstruction，the export image is 16bit(RGB565)per-pixel at 1024×768． (3)The realization of hilgh resolution double buffer memory VGA display controller based on FPGA Using VHDL language constructs double buffer memory VGA display controller,for the import image of 1 6bR(RGB565)per-pixel and flame frequency lower than 20HZ at 1 024x768，implements frequency updating，the format of export image is XGA@160HZ K