基于fpga的3des加密算法的设计-集成电路工程专业论文.docxVIP

摘要 随着网络的不断普及，社会信息化程度的日益提高，信息安全也越来越被重 视。加密技术作为信息安全的一个最为有力的武器，发挥着重要的作用。数据加 密标准（Data Encryption Standard），即 DES 加密算法，及由其延伸出的 3DES 加 密算法是应用最广泛的分组对称加密算法之一。而 FPGA 在实现算法方面具有灵 活性、安全性和很高的速度性能的特点。 本文在分析 DES/3DES 加密算法的基础上，利用流水线技术和分时复用技术， 设计了三种 3DES 加密系统的实现方案，分别是纯组合逻辑结构、流水线结构（包 括 48 级流水线和 12 级流水线）和状态机结构（包括 12 级流水线内复用和 4 级流 水线外复用）。这三种设计方案通过了软件的仿真验证，并以其中一种方案为验证 目标，设计了一种基于 FPGA、以 UART 为通信接口的硬件验证平台，验证了系 统功能的正确性。最后以 FPGA 为实现基础，对上述三种设计方案的速度和使用 资源进行了比较。 概括的说，纯组合逻辑结构方案资源使用较少，但速度过慢；流水线结构方 案获得了很高的数据吞吐量，但资源耗费严重；状态机结构方案结合流水线和分 时复用技术，使速度和资源都能达到可以接受的范围，即起到一定的速度和资源 折中效果。 本文的设计思路方法及三种方案实现结果的比较结论对实际工程具有指导 意义。 关键词： 3DES 流水线 分时复用 UART FPGA Abstract With the rapid development of information technology of the Internet and the society, information security is playing a more and more important role in our daily life. Data Encryption Standard (DES) and its improved algorithm 3DES are one of the most widely used symmetrical block cipher. And FPGA is a preferred method to implement an encryption algorithm for its flexible, security and high speed. The paper introduce the principle of DES/3DES firstly, then based on the principle of pipeline design and time division multiplexing design, the following three implementations of 3DES encryption algorithm are discussed. The first one is designed with pure combinational logic. And the second one is based on pipeline principle, including 48-stage pipeline and 12-stage pipeline. The third one is based on time division multiplexing principle, including multiplexing within the 12-stage pipeline and multiplexing of the whole 4-stage pipeline. The three implementations are all simulated with software. And a hardware verification testbench with UART as its communication interface based on FPGA is designed, aimed at one of the implementation. Finally, a comparison of encryption speed and hardware resource usage is given between the implementation results of the three designs. On the whole, the first design uses less resource but has a very slow speed. The second desi