基于fpga的级联码设计与实现-通信与信息系统专业论文.docxVIP

摘 摘 要 桂林电子科技大学学位论文 桂林电子科技大学学位论文 摘 要 随着计算机和通信技术的飞边发展，数字信息的存储和交换量日益增加，对数据 传输过程中的可靠性要求也越来越高。由于纠错编码可以提高数字传输的可靠性，因 而一直备受关注。级联编码由于有着很强的纠错能力，所以在通信领域得到了广泛的 应用。本文主要研究了由RS码、交织和卷积码组成的级联码的编译码算法及其实现。 在第一、二章中首先介绍了课题的研究意义及其国内外的发展情况，接着对信道 编码定理和差错控制理论作了概述，然后给出了本次设计级联码的编译码方案。 在第三到第五章中我们分别对RS码、卷积码和交织器的原理做了详细的分析，并 且对其编译码的实现算法进行了深入的研究，同时给出了在FPGA中硬件结构的具体 实现方法和仿真结果。在本次设计中，内码卷积码采用viterbi译码，它主要由分支路径 度量、加比选和幸存路径度量等几部分组成;外码RS码采用BM基代算法，它主要由 伴随式的计算、关键方程的求解、钱搜索和Forney算法等几部分组成;而交织器采用 的是分组交织。 关键词:级联码;RS码;卷积码;交织器;Viterbi;FPGA。 万方数据 I – – – PAGE IV – 万方数据 Abstract With the development of computer and communication technology, the storage and exchange amount of digital data increase dramatically, which requires a higher reli- ability for data transmission. Since Error Correcting Code can enhance such reliability, it has been attached importance since the day it came into being. The concatenated code has been widely used in communication field because of its strong ability of error correction. This thesis devotes to the research and realization of concatenated code, which is made up of the Reed-Solomon code, interleaving and the convolution code. In the first and the second chapter, the significance of this design and the de- velopment at home and abroad is introduced first, then the channel coding theorem and the error correction technology are described, finally the system scheme of the concatenated code is introduced. From the third chapter to the fifth, the details of theory for the Reed-Solomon code, interleaving and the convolution code are analyzed, and their concretely algo- rithm are researched deeply. At the same time, the implementation of hardware struc- ture based on FPGA and the result of simulation is described. In this thesis, The Viterbi algorithm was used in convolution decoding, it was constitutive of branch path measurement, Add-compare-select and surviving path measurement; The BM iterative algorithm was used in Reed-Solomon decoding, it was constitutive of syndrome c