面向媒体处理的可重构阵列的结构设计与研究-电路与系统专业毕业论文.docxVIP

I I 面向媒体处理的可重构阵列的结构设计与研究 摘 要 现代媒体处理实时性强、数据量大、计算复杂性高的特点给多媒体 处理器的处理性能带来了很大的挑战。同时，其多标准多协议的特点又 对处理器灵活性提出了一定的要求。可重构处理器作为一种能够兼顾通 用处理器(GPP)的灵活性和专用集成电路(ASIC)高效性的架构，为现代多 媒体处理提供了一种有价值的研究方向。 多媒体处理算法中存在少数循环处理任务占用大量计算时间的规 律，基于这个事实，本文首先分析了多媒体处理 H.264 解码部分中的 IDCT、残差与预测值求和、像素内插等目标算法，并针对算法设计了一 种易于将循环映射到阵列上加速以提高其计算效率的可重构阵列系统， 对这一系统，从处理单元、互连、数据通路、地址译码单元到控制系统 都进行了详细的设计。之后，针对多媒体处理算法计算量大，数据并行 性高的特点，本文分析了多媒体处理中部分算法的位宽需求，在设计中 引入亚字并行技术，同时运算数据的高低位，使得数据的吞吐量增大了 一倍。基于上述设计，本论文提出了将算法映射到阵列上运行的基本流 程和方法，同时设计了配置字生成的图形化工具以方便映射过程。进一 步，论文详细叙述了可重构阵列系统的验证流程，并将部分目标算法映 射到阵列上进行验证，得到了系统的处理性能指标。 关键字：可重构阵列；循环映射；亚字并行计算； II II RESEARCH AND DESIGN OF RECONFIGURABLE ARRAY FOR MULTIMEDIA APPLICATIONS ABSTRACT Modern multimedia process is characterized by high real-timing, large amount of data, and high computational complexity. These require high performance of media processors. Meanwhile, different standards of multimedia process require processors to be more flexible. Reconfigurable processor is a new kind of computing architecture which owns both the high flexibility of GPP and high performance of ASIC. So, it provides a valuable research direction for multimedia processing. Multimedia processing algorithms have a rule that the kernel loops account for most of the execution time of the task. Based on this rule, the paper analyzed the algorithm of multimedia process, such as IDCT transform, the calculation of predicted value and the summation operation, and designed a reconfigurable processing array which loops are easy to be mapped on to accelerate the computing. We designed the whole reconfigurable array system from processing element, interconnect, datapath, address decoder to controller. Also, based on the character of high amount of data and high parallelism of multimedia process, we analyzed the bitwidth requirement of parts of algorithm, and introduced sub-word parallelism technology into the design. The sub-word parallelism array can calculate the higher and lower bits of data at the same time, so that the