基于VHDL语言的8位RISC-CPU的设计 文献翻译.docVIP

PAGE 毕业设计说明书 基于VHDL语言的8位RISC-CPU的设计 学 院： 专 业： 学生姓名： 学 号： 指导教师： 2011年5月 外文翻译（原文） 1 - A RISC Design: Synthesis of the MIPS Processor Core A full die photograph of the MIPS R2000 RISC Microprocessor is shown above. The 1986 MIPS R2000 with five pipeline stages and 450,000 transistors was the world’s first commercial RISC microprocessor. Photograph ?1995-2004 courtesy of Michael Davidson, Florida 14.1 The MIPS Instruction Set and Processor The MIPS is an example of a modern reduced instruction set computer (RISC) developed in the 1980s. The MIPS instruction set is used by NEC, Nintendo, Motorola, Sony, and licensed for use by numerous other semiconductor manufacturers. It has fixed-length 32-bit instructions and thirty-two 32-bit general-purpose registers. Register 0 always contains the value 0. A memory word is 32 bits wide. As seen in Table 14.1, the MIPS has only three instruction formats. Only I- format LOAD and STORE instructions reference memory operands. R-format instructions such as ADD, AND, and OR perform operations only on data in the registers. They require two register operands, Rs and Rt. The result of the operation is stored in a third register, Rd. R-format shift and function fields are used as an extended opcode field. J-format instructions include the jump instructions. Table 14.1 MIPS 32-bit Instruction Formats LW is the mnemonic for the Load Word instruction and SW is the mnemonic for Store Word. The following MIPS assembly language program computes A = B + C. LW $2, B ;Register 2 = value of memory at address B LW $3, C ;Register 3 = value of memory at address C ADD $4, $2, $3 ;Register 4 = B + C SW $4, A ;Value of memory at address A = Register 4 The MIPS I-format instruction, BEQ, branches if two registers have the same value. As an example, the instruction BEQ $1, $2, LABEL jumps to LABEL if