雷达高度表高速数据采集系统设计与实现-通信与信息系统专业论文.docxVIP

华 华 中 科 技 大 学 硕 士 学 位 论 文 I I 摘 要 本文介绍了一种基于 Compact PCI 总线的高速数据采集系统，该系统用于脉冲 雷达高度表视频回波信号的实时采集，也可以用于其他通用的数据采集场合；系统 采样率高达 200MSPS，量化精度 12bit，并且实现了小于 0.3%的模拟信号静态失真 度。 目前，高性能数据采集系统设计和实现的难点并不在于信号的高速采样，而是 在于数据的实时处理、传输和存储；传统的存储介质往往具有速度或者容量方面的 不足，而数据向计算机系统的传输也往往会受到总线速度、操作系统响应延迟等因 素的影响，这些都成为限制数据采集系统性能提高的瓶颈。 经过大量的分析与论证工作，本课题决定采用高性能 FPGA 实现数据的实时处 理，并根据系统的各项参数设计和实现了多级数据缓存系统，实现了 ADC 采样数据 与 Compact PCI 总线之间的适配，然后用 32bit/33MHz 配置的 Compact PCI 总线和 RAID 0 组态的磁盘阵列来实现数据的高速传输和存储。 本文首先对数据采集系统的基本原理和组成结构进行了阐述，然后根据系统的 各项参数要求确定了总体方案，并对各项参数进行了计算和论证；然后用大量的篇 幅对系统的硬件设计、FPGA 逻辑设计、Windows 下驱动程序以及应用程序的设计 和具体实现进行了完整的论述；针对 Compact PCI 总线操作和操作系统中断响应的 特点，对基于 FPGA 片内 RAM、片外 FIFO 和主机物理内存的多级数据缓存系统以 及高效的数据拆分、重组机制系统作了详细阐述。 关键词：高速数据采集，Compact PCI，FPGA，FIR 滤波器 II II Abstract This thesis introduces a kind of high-speed data acquisition system based on the Compact PCI bus, the system is designed for the real-time acquisition of high speed echo wave from pulse radar altimeter, it can also be used for other general occasions of data collection. The system provides a sampling rate of up to 200MSPS, a quantize precision of 12 bit, and achieved less than 0.3% of the analog signal static distortion. Currently, the difficulty in design and implementation of high performance data acquisition system design does not lie in the high-speed analog signal sampling, but in the section of real-time data processing, transmission, and storage; traditional storage media often have deficiencies on speed or capacity, and speed of data transmission to computer system transmission is also limited by several factors, such as bus speed of computer system and response latency of operating system, these are the main bottlenecks that limit the performance improvement of data acquisition system. After much study and analysis, the subject decide to use FPGA to complete the real-time data processing task, a multi-level cache system was then designed to achieve the fit between sampling data from high speed ADC and Compact PCI bus, then a