CMOS制造工艺流程简介.ppt

2.1 CMOS制造工艺流程简介 We will describe a modern CMOS process flow. Process described here requires 16 masks and 100 process steps. 第二章 CMOS制备基本流程 Stages of IC Fabrication ? In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated below. CMOS Digital Gates 反相电路 或非门：同时输入低电平时才能获得高电平输出 PMOS and NMOS wafer cross section after fabrication 2-Level Metal CMOS 两层互连布线的CMOS 有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。 对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。 ? ? ? ? ? ? ? ? Choosing a Substrate Active Region N and P Well Gate Tip or Extension Source and Drain Contact and Local Interconnect Multilevel Metalization Processing Phases 1 μm Photoresist 40 nm SiO2 Choose the substrate (type, orientation, resistivity, wafer size) ? Initial processing: - Wafer cleaning - thermal oxidation, H2O (≈ 40 nm, 15 min. @ 900oC) - nitride LPCVD (低压化学气相沉积) (≈ 80 nm @ 800oC) ? Substrate selection: - moderately high resistivity (25-50 ohm-cm) - (100) orientation - P- type. 80 nm Si3N4 Choosing a Substrate Si,(100), P Type,25~50Ωcm 1st Mask Photoresist ? spinning and baking @ 100oC (≈ 0.5 - 1.0 μm) 2.2 有源区的形成 ? Photolithography - Mask #1 pattern alignment and UV exposure - Rinse away non-pattern PR - Dry etch the Nitride layer -- Plasma etch with Fluorine CF4 or NF4 Plasma - Strip Photoresist (H2SO4或O2 plasma) Active Area Definition (主动区) SiO2 Si3N4 Photoresist ? Wet Oxide (thick SiO2) - H2O (≈ 500 nm, 90 min. @1000oC) ? Strip Nitride layer - Phosophoric acid (磷酸) or plasma etch，选择性问题 Field Oxide Growth - LOCOS: Local Oxidation of Silicon (局部硅氧化工艺) SiO2 Si3N4 ? 薄的SiO2层，厚的Si3N4层，避免鸟喙(bird’s beak)的影响 ? 场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。 ? Photolithography (套刻) - Mask #2 pattern alignment and UV exposure ? Ion Implantation 离子注入 - B+ ion bombardment Penetrate thin SiO2 and field SiO2 -- 反型：半导体表面的少数载流子浓度等于体内的多数载流