第十七讲未来趋势与挑战.pptVIP

* Top view Cross section Wafer SiO2 poly-Si Si0.2Ge0.8 SiN SiN STL的工艺流程，3 * Top view Cross section Wafer SiO2 poly-Si SiN Resist STL的工艺流程，4 * Top view Cross section Wafer SiO2 poly-Si SiN Resist STL的工艺流程，5 * Top view Cross section Wafer SiO2 poly-Si SiN Resist STL的工艺流程，6 * Top view Cross section Wafer SiO2 poly-Si STL的工艺流程，7 SiN * 10 poly-Si lines Width=45 nm poly-Si contact H=15 nm W=15 nm poly-Si NiSi 50nm 150nm Si STL的工艺流程，8 * Fin W=35 nm Fin H=27 nm L=70 nm Zhang Qiu et al. IEEE EDL May 2008 Al wiring Contact holes to S/D Double Fin channel Gate FinFET produced using STL twice * 常规光刻技术和标准硅薄膜工艺技术的革新和结合 对细线条而言，理论上 k1?0 Pitch的大小由常规光刻技术的分辨率决定 常规光刻技术的使用保证了高产率 “侧墙转移”( STL)的特征和优点 * 2n lines after n iterations of spacer lithography! 1st Spacers 2nd Spacers 3rd Spacers 运用STL技术产生高密度图形 Photo-lithographically defined sacrificial structures Y.-K. Choi et al., JVST-B 21, 2951-2955 (2003) * STL工艺中线条尺寸的控制 CVD技术淀积的薄膜具有超常均匀性和可控性 STL纳米线的线宽由SiN薄膜决定 STL纳米线的线厚由poly-Si薄膜决定 Choi et al., IEEE T-ED 49, 436（2002） Lg Lg STL技术得到的栅 ? 均匀的 Lg 通常光刻技术 制备的栅 ? 不均匀的 Lg * STL EB ArF Kaneko et. al., IEDM2005 用STL制备线条的线宽不均匀性非常小 ! STL * Summary Ideal Optical EBL NIL STL Resolution Good Good Good Good Good Pattern shape Any Any Any Any Lines/ Rings Largesmall patterns Yes Yes No Yes Yes Alignment Good Good Good Poor Good Throughput High High Low Medium High Initial cost Low High Medium Low Low Running cost Low High Low Medium Low * 预祝考试成功！考试时间： 2010.07.09.下午1:30 – 3:30地点：Z2108教室答疑时间：10:00 – 14:30，2010.07.07地点：Z2307B （助教负责） * * During this lecture I will describe lithography techniques that enables printing of feature sizes less than 100 nm on a wafer. * * * * During this lecture I will describe lithography techniques that enables printing of feature sizes less than 100 nm on a wafer. * So we would like…. * The major drawback is that the direct writing is time consuming and methods to increase throught like…… * The major drawback is that the direct writing is time c