可编程实验报告-VHDL.doc

实验1 74ls157 4二选一选择器 library ieee; use ieee.std_logic_1164.all; entity ls157 is port (a1,a2,a3,a4,b1,b2,b3,b4,g : IN STD_LOGIC; y1,y2,y3,y4 : OUT STD_LOGIC); end; architecture one of ls157 is begin process(g) begin if g=0 then y1=a1;y2=a2;y3=a3