集成电路VHDL课件 第(7)章.pptVIP

7.1 一般有限状态机设计 7.1 一般有限状态机设计 8.2 Moore型有限状态机设 7.2 Moore型有限状态机设 Mealy型有限状态机的设计 【例】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY1 IS PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END MEALY1; ARCHITECTURE behav OF MEALY1 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL STX : states ; BEGIN COMREG : PROCESS(CLK,RESET) BEGIN --决定转换状态的进程 IF RESET =1 THEN STX = ST0; ELSIF CLKEVENT AND CLK = 1 THEN 接下页 CASE STX IS WHEN st0 = IF DATAIN = 1 THEN STX = st