DC培训教程(英文版).pptVIP

1Design Compiler for Chip Synthesis 2AgendaIntroduction to SynthesisSetup, Library and ObjectsTiming and AreaEnvironmental AttributesOptimizationCompile Strategies 3AgendaIntroduction to SynthesisSetup, Library and ObjectsTiming and AreaEnvironmental AttributesOptimizationCompile Strategies 4Design FlowYou are here! 5(read)(compile) 6Introduction to DC The Design Compiler product is the core of the Synopsys synthesis software products. It comprises tools that synthesize your HDL designs into optimized technology-dependent,gate-level designs. It supports a wide range of flat and hierarchical design styles and can optimize bothcombinational and sequential designs for speed, area and power. 7Synthesis Is Constraint-DrivenYou set the goals (through constraints).Synthesis tool optimizes the design to meet your goals flatten 8Synthesis Is Path-BasedDesign Compiler uses Static Timing Analysis (STA) to calculate the timing of the paths in the design Synthesis tool summaryASIC synthesis tools: Synopsys: Design Compiler, Design Vision, Design Analyzer Magma: Blast Fusion Cadence: BuildGatesFPGA synthesis tools:Synplicity: SymplifyXilinx: ISEAltera: Quartus9 10AgendaIntroduction to SynthesisSetup, Library and ObjectsTiming and AreaEnvironmental AttributesOptimizationCompile Strategies Setup, Library and ObjectsProject Directory Preparation11 .synopsys_dc.setupSoftware install directoryUser’s General Setup directoryUser’s Specific Project Setup directory: 三个setup文件依次执行,后者可以覆盖前者的定义Commands in .synopsys_dc.setup are executed upon tool startup .synopsys_dc.setupsearch_pathtarget_librarylink_librarysymbol_library13 14Target LibraryThe target library is the library used by DC for building a circuit during compileDuring mapping, DC will: 1. Choose functionally-correct gates from this library 2. Calculate the timing of the circuit using vendor-supplied timing data for these gates 15Link LibraryUsed to resolve leaf-cells and subdesign