Lecture 18 VLIW and EPIC.ppt

Fast Cache Hit by Virtual Cache Physical Cache – physically indexed and physically tagged cache Virtual Cache – virtually indexed and virtually tagged cache Must flush cache at process switch, or add PID Must handle virtual address alias to identical physical address Fast Cache Hits by Avoiding Translation: Process ID impact Black is uniprocess Light Gray is multiprocess when flush cache Dark Gray is multiprocess when use Process ID tag Y axis: Miss Rates up to 20% X axis: Cache size from 2 KB to 1024 KB Virtually Indexed, Physically Tagged Cache What motivation? Fast cache hit by parallel TLB access No virtual cache shortcomings How could it be correct? Require cache way size = page size; now physical index is from page offset Then virtual and physical indices are identical ? works like a physically indexed cache! What if want bigger caches? Higher associativity moves barrier to right Page coloring Pipelined Cache Access For multi-issue, cache bandwidth affects effective cache hit time Queueing delay adds up if cache does not have enough read/write ports Pipelined cache accesses: reduce cache cycle time and improve bandwidth Cache organization for high bandwidth Duplicate cache Banked cache Double clocked cache Key technology: Wave pipelining that does not need latches Pipelined Cache Access Alpha 21264 Data cache design The cache is 64KB, 2-way associative; cannot be accessed within one-cycle One-cycle used for address transfer and data transfer, pipelined with data array access Cache clock frequency doubles processor frequency; wave pipelined to achieve the speed Trace Cache Trace: a dynamic sequence of instructions including taken branches Traces are dynamically constructed by processor hardware and frequently used traces are stored into trace cache Example: Intel P4 processor, storing about 12K mops (End of cache) Two Paths to High ILP Modern superscalar processors: dynamically scheduled, speculative execution, branch prediction, dynamic memory disambi