具有三态输出单总线缓冲器门.pdfVIP

SGES002A − APRIL 2003 − REVISED MAY 2004 Qualification in Accordance With Ioff Supports Partial-Power-Down Mode AEC-Q100† Operation Qualified for Automotive Applications Latch-Up Performance Exceeds 100 mA Customer-Specific Configuration Control Per JESD 78, Class II Can Be Supported Along With ESD Protection Exceeds JESD 22 Major-Change Approval − 2000-V Human-Body Model (A114-A) Available in the Texas Instruments − 200-V Machine Model (A115-A) NanoStar and NanoFree Packages − 1000-V Charged-Device Model (C101) Supports 5-V VCC Operation DCK PACKAGE Inputs Accept Voltages to 5.5 V (TOP VIEW) Max tpd of 3.7 ns at 3.3 V OE 1 5 VCC Low Power Consumption, 10-µA Max ICC A 2 ±24-mA Output Drive at 3.3 V GND 3 4 Y † Contact factory for details. Q100 qualification data available on request. description/ordering information This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devic