ppt课件-c s152 computer architectureand engineering- soda hall（c s152计算机建筑与工程-苏打大厅）.pptVIP

CS152Computer Architecture and EngineeringLecture 4Performance, Delay, and Cost Continued February 5, 2003 John Kubiatowicz (/~kubitron) lecture slides: /~cs152/ Review: Performance and Technology Trends Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year Feature Size: shrinks 10% / yr. = Switching speed improves 1.2 / yr. Density: improves 1.2x / yr. Die Area: 1.2x / yr. RISC lesson is to keep the ISA as simple as possible: Shorter design cycle = fully exploit the advancing technology (~3yr) Advanced branch prediction and pipeline techniques Bigger and more sophisticated on-chip caches Review: Amdahls Law Speedup due to enhancement E: ExTime w/o E Performance w/ E Speedup(E) = -------------------- = -------------------------- ExTime w/ E Performance w/o E Suppose that enhancement E accelerates a fraction F of the task by a factor S and the remainder of the task is unaffected then, ExTime(with E) = ((1-F) + F/S) X ExTime(without E) Speedup(with E) = 1 (1-F) + F/S Review: General C/L Cell Delay Model Combinational Cell (symbol) is fully specified by: functional (input - output) behavior truth-table, logic equation, VHDL load factor of each input critical propagation delay from each input to each output for each transition THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load Linear model composes Basic Technology: CMOS CMOS: Complementary Metal Oxide Semiconductor NMOS (N-Type Metal Oxide Semiconductor) transistors PMOS (P-Type Metal Oxide Semiconductor) transistors NMOS Transistor Apply a HIGH (Vdd) to its gateturns the transistor into a “conductor” Apply a LOW (GND) to its gateshuts off the conduction path PMOS Transistor Apply a HIGH (Vdd) to its gate shuts off the conduction path Apply a LOW (GND) to its gate turns the transistor into a “conductor” Basic Components: CMOS Inverter Inverter O