ppt课件-c s e241 v l s i digital circuits winter2003 lecture03 a s i c（c s e241 v l s我数字电路winter2003 lecture03年代我c）.pptVIP

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ppt课件-c s e241 v l s i digital circuits winter2003 lecture03 a s i c（c s e241 v l s我数字电路winter2003 lecture03年代我c）.ppt

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CSE241VLSI Digital CircuitsWinter 2003Lecture 06: Timing This Class + Logistics Timing Storage elements, Clock distribution, Clock tree synthesis Reading Whitepapers/datasheets on STA; papers on clock tree synthesis Schedule MT in one week (lab/recitation fair game); Lab #2 due Mon 1/27 HW #9: As a block’s layout is compacted down to fit into a smaller and smaller region, the timing of the block at first improves, but then worsens. Explain. HW #10: Hold time violations mean that the chip doesn’t work at any frequency. Propose several distinct methods for fixing hold time violations (guided by post-routing static timing analysis), and explain the pros and cons of each. HW #11: Compare DEC’s first Alpha and first StrongArm processors (look up transistor counts, supply voltage, frequency, etc.). (a) How much of StrongArm’s power efficiency can be attributed to process, supply, and frequency scaling? (b) What factors might contribute to the remainder? Review Static timing analysis (Lecture 4) Pin-based timing graph Directed acyclic graph (DAG) of timing arcs Longest path in DAG ? time linear in #arcs (edges) Slack = required arrival time – actual arrival time (long path analysis) Logic synthesis (Lecture 5) Static Analysis vs. Dynamic Analysis Enhancements of STA Incremental timing analysis Nanometer-scale process effects – variation (? probabilistic timing analysis) Interference – crosstalk Multiple inputs switching Conservatism of delay propagation (Old: HW #8: Suppose you change the size of one (combinational) gate in your design, thus invalidating the previous timing analysis. How much work must be done to regain a correct timing analysis?) Timing Correction Driven by STA “Incremental performance analysis backplane” Fix electrical violations Resize cells Buffer nets Copy (clone) cells Fix timing problems Local transforms (bag of tricks) Path-based transforms Local Synthesis Transforms Resize cells Buffer or clone to reduce load on critical