电子科技大学《数字逻辑设计及应用》Lec10-Chap 6.pptVIP

Jin. UESTC Digital Logic Design and Application * Digital Logic Design and ApplicationLecture #10 Combinational Logic Design Practices Documentation Standard and Circuit Timing UESTC, Spring 2013 * Chapter 6 Combinational Logic Design Practices How to conceive a complex system? –– structured thinking Some useful combinational components * 6.1 Documentation Standard A documentation package contain the following items: Specification: description of interface and function Block diagram: system’s major function module and their basic interconnections Schematic diagram （P360 Figure 6-17） Timing diagram （P363 Figure 6-19） Structured logic device description Circuit description: explains how the circuit works internally * schematic diagram * 1. Block Diagrams A block diagram shows the inputs, outputs, functional modules, internal data paths, and important control signals of a system. P345 Figure 6-1 * 2. Gate Symbols * Equivalent Gate Symbols underthe Generalized Demorgan’s Theorem inverter buffer AND NAND NOR OR OR NOR NAND AND * 3. Active Levels active level active high and active low asserted: a signal is at its active level negated / deasserted: signal is not at its active level signal name Active levels for pins Logic Functions are performed inside the symbolic outlines. READY REQUEST GO READY_L REQUEST_L GO_L Indicate an Active-Low Pin 与门和或门的输入为1才能确保其输出 * Example: active levels A B F Signal active state: switch—off, lamp—light A B F 0 0 0 0 1 0 1 0 0 1 1 1 Switch: 1－off Lamp: 1－light A B F Switch: 0－off Lamp: 0－light A B F 0 0 0 0 1 1 1 0 1 1 1 1 A B F F = A + B = ( A’ · B’ )’ AND: the output is asserted if and only if all its inputs are asserted. Positive Logic 1：High Level 0： Low Level Active High Active Low * Example: active levels A B F Active state: switch—off, lamp—light AND: