efficient hardwaresoftware implementation of lpc algorithm in speech coding applications高效hardwaresoftware lpc算法在语音编码应用程序的实现.pdfVIP

Journal of Signal and Information Processing, 2012, 3, 122-129 /10.4236/jsip.2012.31016 Published Online February 2012 (http://www.SciRP.org/journal/jsip) Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications Mohamed Atri, Fatma Sayadi, Wajdi Elhamzi, Rached Tourki Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia. Email: {Mohamed.Atri, Rached.Tourki}@fsm.rnu.tn, {Sayadi_Fatma, Elhamziwajdi}@yahoo.fr Received January 2nd, 2011; revised September 14th, 2011; accepted November 3rd, 2011 ABSTRACT The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The window- ing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths. Keywords: Linear Predictive Coding; System on Programmable Chip; FPGA; Co-Design 1. Introduction ferent versions on an FPGA. The system performances have been evaluated with a prototyping board integrating Applications such as cell phones, hearing aids, and digi- embedded Microblaze processor wit